Digital electronic circuits generally employ two-state output terminals to convey binary logic information. Such two-state output terminals produce one of two output voltages: a relatively high-voltage, or a relatively low-voltage. These two discernable voltages define two possible binary logic states. The low-voltage defines a "0," "false," or "low" logic state. The high-voltage defines a "1," "true," or "high" logic state. A voltage corresponding to a "low" is defined to be below a first threshold voltage and a voltage corresponding to a "high" is defined to be above a second, higher, threshold voltage. A voltage between the first and second thresholds is not a valid logic state, and is avoided (except during transitions between valid states) by the specific operational parameters of the electronic devices formed in the integrated circuit or other digital circuitry.
Output terminals of digital circuitry, and integrated circuits in particular, can be constructed to produce a third state. This additional or third state is not defined by a voltage level, but instead is indicated by a high-impedance state at the signal terminal. Such a high-impedance signal state is assumed during certain operations or under specified conditions. For example, in memory integrated circuits a high-impedance state has been used on a data terminal to indicate failure during a testing mode of operation.
The high-impedance state or "tri-state" does not usually correspond to a logic state. In some memory chips, such a high-impedance state is useful where multiple data terminals are to be electrically connected to a common data bus. The memory of the associated computer control circuitry allows a single memory chip to operate while the data terminal of other chips are placed in a high-impedance state. Thus, multiple output terminals from numerous devices may be connected to a single input terminal, with control circuitry selecting which of the output terminals is to be active at any given time. However, the high-impedance signal state of a three-state signal terminal can also be used to convey information.
A dynamic random access memory integrated circuit (DRAM) is an example of one type of circuit which can be designed to use a three-state signal terminal to convey a third information state. This third, high-impedance state is in addition to high and low voltage logic states. During testing, a DRAM is put into a test mode to enable reading from and writing to a group of memory storage cells during a single read or write access cycle. In specific, during a single test mode write access cycle a known logic state is presented to a data input/output terminal of a DRAM. This state is written in parallel to a number of individual memory storage cells to speed testing. During an associated test mode read cycle, the logic states from each of the group of memory storage cells is read and internally compared within the integrated circuit. If they are identical, the logic state stored by the group of cells is produced at the data input/output terminal. Otherwise, a high-impedance state is produced.
Unfortunately, conventional two-state logic testing apparatus are not able to determine whether a signal terminal is producing a high-impedance state. The high-impedance state is not defined by a specific voltage or even a range of voltages. Because a terminal at a high impedance is effectively shut off from internal chip circuitry, the terminal may assume various voltages. The high-impedance terminal voltage may be limited by external factors such as external terminal biasing. Two-state logic testing apparatus have input terminals which are only capable of determining whether a voltage corresponds to a low or a high logic state. Since the voltage of a high-impedance terminal may assume various voltages, and the two-state logic tester cannot indicate an invalid voltage, direct detection of a high-impedance output state is impossible using a two-state testing apparatus.
To test such three-state circuits more expensive and complicated testing equipment has previously been necessary. Instead of using relatively less expensive two-state comparative digital testing devices, it has been necessary to use complicated analog circuit testing equipment which must be accurate to more specific voltages. The analog testers use additional circuitry referred to as window detectors to make the correct determination of the high-impedance state. A window detector is an analog comparator circuit which determines whether a voltage at a signal terminal is within a specified analog range. The window detector determines whether the voltage at the signal terminal is between the high and low thresholds. Such analog window-detection testing equipment has been used by externally biasing a three-state signal terminal to a middle voltage between the logic thresholds. Output of high and low logic states during testing overcomes the applied middle or intermediate voltage bias thus causing the terminal to assume the appropriate logic state voltage. Output of a high-impedance signal state results in the terminal maintaining the intermediate voltage which is detected by the relatively more complicated analog testing equipment. Presence of the intermediate voltage at the signal terminal thus indicates the high-impedance state.
Window detectors and analog test circuitry are relatively more expensive than digital, two-state test equipment. Semiconductor manufacturers and others continue to have a strong need for improved testing techniques involving circuits with terminals which assume high-impedance states. Testing is a significant part of integrated circuit manufacture. In high capacity memory chips this occurs because millions of cells must be tested in each chip to assure accurate data storage and retrieval. The current invention is a substantial improvement in the art of testing of digital devices which include digital terminals having a high-impedance output state.